Verilog HDL Design Examples
tet 2017 · CRC Press
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The Verilog language provides a means to model a digital system at many levels of abstraction from a logic gate to a complex digital system to a mainframe computer. The purpose of this book is to present the Verilog language together with a wide variety of examples, so that the reader can gain a firm foundation in the design of the digital system using Verilog HDL. The Verilog projects include the design module, the test bench module, and the outputs obtained from the simulator that illustrate the complete functional operation of the design. Where applicable, a detailed review of the theory of the topic is presented together with the logic design principles—including: state diagrams, Karnaugh maps, equations, and the logic diagram. Numerous examples and homework problems are included throughout. The examples include logical operations, counters of different moduli, half adders, full adders, a carry lookahead adder, array multipliers, different types of Moore and Mealy machines, and arithmetic logic units (ALUs).
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Joseph Cavanagh received his Bachelor of Science in Electrical Engineering from Indiana Institute of Technology and his Master of Science from Santa Clara University. He spent twenty-two years teaching in the Department of Computer Engineering at Santa Clara University. Prior to that, he taught in the Computer Engineering Department at San Jose State University. Currently, he is an Associate Professor in the Department of Electrical Engineering at Cogswell Polytechnical College, where he has been for the past twelve years. Additionally, he has over two decades of experience designing computing equipment--including arithmetic processors, instruction fetch units, and peripheral control units--for such companies as International Business Corporation, Amdahl Corporation, and Digital Equipment Corporation. Joseph Cavanagh is a member of IEEE, IEEE Computer Society, Tau Beta Pi, and the author of six publications.
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