Substrate Noise Coupling in RFICs
ΠΌΠ°ΡΡ 2008β―Π³. Β· Springer Science & Business Media
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ΠΡΠ·ΡΠ²Ρ: 4report
ΠΠ»Π΅ΠΊΡΡΠΎΠ½Π½Π°Ρ ΠΊΠ½ΠΈΠ³Π°
119
ΠΠΎΠ»ΠΈΡΠ΅ΡΡΠ²ΠΎ ΡΡΡΠ°Π½ΠΈΡ
reportΠΡΠ΅Π½ΠΊΠΈ ΠΈ ΠΎΡΠ·ΡΠ²Ρ Π½Π΅ ΠΏΡΠΎΠ²Π΅ΡΠ΅Π½Ρ. ΠΠΎΠ΄ΡΠΎΠ±Π½Π΅Π΅β¦
ΠΠ± ΡΠ»Π΅ΠΊΡΡΠΎΠ½Π½ΠΎΠΉ ΠΊΠ½ΠΈΠ³Π΅
Substrate noise coupling in integrated circuits (ICs) is the process by which int- ference signals in the form of voltage and current glitches cause parasitic currents to ?ow in the silicon substrate to various parts of the IC. The source of such glitches and parasitic currents could be from the switching noise of high speed digital clocks on the same chip. In RF and mixed signal ICs the switching noise is coupled to sensitive analog and RF nodes in the IC causing degradation in performance that could severely impact the yield. Thus, overcoming substrate coupling is a key issue in successful βsystem on chipβ ?rst-pass integration where RF and mixed signal blocks, high speed digital I/O interface are integrated with digital signal proce- ing algorithms on the same chip. This is particularly true as we move to sub-90 nanometer system on chip integration. In this book a substrate aware design ?ow is built, calibrated to silicon and used as part of the design and validation ?ows to uncover and ?x substrate coupling problems in RF ICs. The ?ow is used to develop a comprehensive RF substrate noise isolation design guide to be used by RF designers during the ?oor planning, circuit design and validation phases. This will allow designers to optimize the - sign, maximize noise isolation and protect sensitive analog/RF blocks from being degraded by substrate noise coupling.
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ΠΠ± Π°Π²ΡΠΎΡΠ΅
Mohammed Ismail is the Springer Series Advisor for the Analog Circuits and Signal Processing book series
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