In-/Near-Memory Computing
Daichi Fujiki · Xiaowei Wang · Arun Subramaniyan · Reetuparna Das
svi 2022. · Springer Nature
E-knjiga
124
str.
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O ovoj e-knjizi
This book provides a structured introduction of the key concepts and techniques that enable in-/near-memory computing. For decades, processing-in-memory or near-memory computing has been attracting growing interest due to its potential to break the memory wall. Near-memory computing moves compute logic near the memory, and thereby reduces data movement. Recent work has also shown that certain memories can morph themselves into compute units by exploiting the physical properties of the memory cells, enabling in-situ computing in the memory array. While in- and near-memory computing can circumvent overheads related to data movement, it comes at the cost of restricted flexibility of data representation and computation, design challenges of compute capable memories, and difficulty in system and software integration. Therefore, wide deployment of in-/near-memory computing cannot be accomplished without techniques that enable efficient mapping of data-intensive applications to such devices,without sacrificing accuracy or increasing hardware costs excessively. This book describes various memory substrates amenable to in- and near-memory computing, architectural approaches for designing efficient and reliable computing devices, and opportunities for in-/near-memory acceleration of different classes of applications.
O autoru
Daichi Fujiki received his B.E. degree from Keio University, Tokyo, Japan, in 2016 and his M.S.Eng. degree from the University of Michigan, Ann Arbor, MI, in 2017. He is currently pursuing a Ph.D. in Computer Science and Engineering with the University of Michigan, Ann Arbor, MI. He is a member of the Mbits Research Group, Computer Engineering Laboratory (CELAB), University of Michigan, which develops in-situ compute memory architectures and custom acceleration hardware for bioinformatics workloads.Xiaowei Wang received his B.Eng. degree in Electronic Information Science and Technology from Tsinghua University, Beijing, China, in 2015. He received his M.S. degree in Computer Science and Engineering from the University of Michigan, Ann Arbor, MI, in 2017, where he is currently pursuing a Ph.D. in Computer Science and Engineering. He is advised by Prof. Reetuparna Das. His research interests include domain-specific architectures for machine learning, in-memory computing, and hardware/software co-design.Arun Subramaniyan received his B.E (Hons.) in Electrical and Electronics from the Birla Institute of Technology and Science (BITS-Pilani), India in 2015. He is currently a Ph.D. student at the University of Michigan, advised by Prof. Reetuparna Das. His dissertation research focuses on developing efficient algorithms and customized computing systems for precision health. He is also interested in in-memory computing architectures and hardware reliability. His work has been recognized by UM’s Precision Health Scholars Award, a Rackham International Students Fellowship, an IEEE Micro Top Picks Award, and a Best Paper Award in CODESCISSS.Reetuparna Das received her Ph.D. in Computer Science and Engineering from the Pennsylvania State University, University Park, PA, in 2010. She was a Research Scientist with the Intel Labs, Santa Clara, CA, and the Researcher-In-Residence with the Center for Future Architectures Research, Ann Arbor, MI. She is currently an Associate Professor with the University of Michigan, Ann Arbor. Some of her recent projects include in-memory architectures, custom computing for precision health and AI, fine-grain heterogeneous core architectures for mobile systems, and low-power scalable interconnects for kilo-core processors. She has authored over 45 articles and holds 7 patents. Prof. Das received two IEEE top picks awards, the NSF CAREER Award, the CRA-W’s Borg Early Career Award, the Intel Outstanding Researcher Award, and the Sloan Foundation Fellowship. She has been inducted into IEEE/ACM MI CRO and ISCA Hall of Fame. She served on over 30 technical program committees and as the Program Co-Chair for MICRO-52./div
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