Evolutionary Algorithms for VLSI CAD

Formal Verification of Circuits

Advanced Formal Verification

High Quality Test Pattern Generation and Boolean Satisfiability

Debugging at the Electronic System Level

Formal Specification Level: Concepts, Methods, and Algorithms

In-Memory Computing: Synthesis and Optimization

Towards a Design Flow for Reversible Logic

Quality-Driven SystemC Design

Design for Testability, Debug and Reliability: Next Generation Measures Using Formal Techniques

Formal and Practical Techniques for the Complex System Design Process using Virtual Prototypes: Better Early than Never

Automated Analysis of Virtual Prototypes at the Electronic System Level: Design Understanding and Applications

Robustness and Usability in Modern Design Flows

Binary Decision Diagrams: Theory and Implementation

Exact Design of Digital Microfluidic Biochips

Automatic Methods for the Refinement of System Models: From the Specification to the Implementation

Design Automation Techniques for Approximation Circuits: Verification, Synthesis and Test

Towards One-Pass Synthesis

Enhanced Virtual Prototyping for Heterogeneous Systems

Automated Validation & Verification of UML/OCL Models Using Satisfiability Solvers